FIG. 1 is a diagram illustrating the pin configuration of a standard 48-pin TSOP1 circuit that may be used in a general NAND flash memory device. As shown in FIG. 1, the standard 48-pin TSOP1 includes a plurality of control pins such as /WE, ALE, CLE, /CE, /RE, and R/BB, power pins Vcc and Vss, and input/output pins I/O0˜I/O7. As is well known, data that is to he programmed into the flash memory device is input through the input/output pins I/O0˜I/O7 in synchronization with a transition (e.g. a rising edge or a falling edge) of a control signal /WE. Data that is to be read from the flash memory device is output through the input/output pins I/O0˜I/O7 in synchronization with a transition of the control signal /RE.
The quantity of data that is input into or output from a NAND flash memory device may increase in proportion to the capacity of the NAND flash memory device. Accordingly, as the capacity of NAND flash memory devices increases, all else being equal, the time required to transfer data between the NAND flash memory device and a flash controller may increase. For example, the time required to transfer data between a flash controller and a NAND flash memory device having a 1 kilobyte page size will be twice the time required to transfer data between a flash controller and a NAND flash memory device having a 512-byte page size. Accordingly, as the capacity of NAND flush memory devices has increased, efforts have been made to reduce the data transmission time between the NAND flash memory device and the flash controller.
U.S. Patent Publication No. 2006-0023499 entitled “NON-VOLATILE MEMORY DEVICE FOR PERFORMING DDR OPERATION IN DATA OUTPUTTING PROCESS AND DATA OUTPUTTING METHOD OF THE SAME CAPABLE OF OUTPUTTING DATA AT FALLING EDGE AS WELL AS RISING EDGE OF READ CONTROL SIGNAL”, which claims priority from Korean Patent No. 10-0546418, describes one such effort at reducing the data transmission time. In particular, the above-referenced documents describe data transmission techniques in which data is transferred in synchronization with both the rising and falling edges of the control signal /RE. Both the above-referenced U.S. patent publication and the Korean patent from which it claims priority are incorporated herein by reference as if set forth in their entireties.
According to the above-referenced documents, data read out through a page buffer circuit of a non-volatile memory device is output externally in synchronization with the rising and falling edges of a clock signal (e.g., S_REB) that oscillates in a half cycle of the signal /RE. Such a data output scheme enables data to be rapidly output from the NAND flash memory device to, for example, a flash controller. However, using the signal /RE to generate a clock signal may cause problems.
In particular, as shown in FIG. 1, in the standard 48-pin TSOP1 chip, the signal /RE is supplied through a control pin that is on one side of the chip and data is input and output through the input/output pins I/O0˜I/O7 that are on the other side of the chip. As shown in FIG. 2, the signal /RE that is input to the chip is converted into the clock signal S_REB by a clock generator 10 (the clock generator 10 corresponds to the frequency controller 553 of the forgoing disclosure). The clock signal S_REB is applied to a data buffer circuit 20 that is adjacent to the input/output pins I/O0˜I/O7. The data buffer circuit 20 outputs-data in synchronization with the rising and falling edges of the clock signal S_REB. As shown in FIG. 2, the signal /RE is transferred to the data buffer circuit 20, which is on the right side of the chip, from a pin on the left-side of the chip. With this configuration, it may be difficult to maintain a duty ratio of the signal /RE (from which the clock signal S_REB is generated) at a fixed value (e.g., 50%). As a result, setup/hold margins may be different between data output in synchronization with a rising edge of the clock signal S_REB and data output in synchronization with a falling edge of the clock signal S_REB. Thus, it may be difficult to practically implement a NAND flash memory device with a double data rate (DDR) function using the control signal /RE.